There is a good Article from Daniel Payne over on Semiwiki about the challenges of managing the ever increasing amount of IP in an SoC design. Which according to Semico is now averaging over 100 IP blocks per design, and continuing the increase rapidly.
The key take-away from the article is that it is no longer possible to manage design IP design in an ad-hoc fashion using tools like Excel to track IP status. As designs become more complex, standards continue to evolve, and designs migrate to new nodes – IP is changing so often throughout the design cycle that without well defined and codified processes, the risk of failure is not acceptable. Daniel also discusses how Methodics tools address this IP management challenge.