At the event, our customers were able to network with fellow IC designers and IP management experts, find out how others are using Methodics solutions, share ideas, methodologies, and best practices, and review and provide valuable feedback to us regarding our product roadmap.

The many topics covered during the two day event included:

  • Analog IP reuse
  • Corporate IP Cataloging with Percipient
  • Continuous Integration Flows for IP-centric design
  • IP-centric SOC assembly
  • Managing Variants in an IP-centric environment
  • 3rd Party IP Acceptance Testing & Quality Management
  • Having a common platform for both 3rd party and internal IP development and validation
  • Design Traceability for ISO26262 and other requirements

For reference, here is the agenda we covered during the two day event:

Agenda – Day 1

9:00 – Coffee, Meet and Greet

9:30 – Industry Vision Presentation
“Semiconductor Landscape 2020”
Simon Bennett, Director, R&D Strategy Enabling, Intel

10:00 – Customer Presentations

  • “Working Towards Trunk-Based IP Management”
    Maxim Integrated
  • “Enabling Global Design Infrastructure”,
    Analog Devices Inc.
  • “IP Versions, Hierarchy, Workspaces, Security, and Development Workflows”
    Silicon Labs

12:00 – Lunch provided by Methodics
1:00 – Customer Panel Discussion
1:30 – Round Table Discussions on Common Challenges
4:00 – Round Table Summaries
5:00 – Daily Wrap-Up
5:30 – Private Happy Hour on the patio at the Faultline Brewing Company in Sunnyvale, sponsored by our PLM Partner, Siemens!

Agenda – Day 2

9:00 – Coffee, Meet and Greet
9:30 – Methodics R&D Discussion based on Day 1 Customer Input
11:00 – Methodics R&D Roadmap Presentation and Discussion
12:00 – Lunch provided by Methodics
1:00 – Break-Out Sessions
5:00 – Meeting Wrap-Up and Adjourn

For more details on the event, the presentations, or on the upcoming 2019 Methodics User Group meeting, please contact us.