New Security Standard Seeks to Eliminate Exploitable Vulnerabilities from Chip Designs
San Francisco, CA, August 7, 2019 – Methodics Inc, the leader in Intellectual Property Lifecycle Management (IPLM) and traceability solutions for semiconductor design, today announced that it has become a member of Accellera Systems Initiative and will be an active participant in the Accellera IP Security Assurance Working Group (IPSA WG).
Accellera is an independent, not-for profit organization dedicated to create, support, promote, and advance standards for use by the worldwide electronics industry. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera are contributed to the IEEE for formal standardization and ongoing governance.
Semiconductor companies around the world use the standards developed by Accellera in a wide range of projects in numerous application areas for the development of consumer, mobile, wireless, automotive, and other “smart” electronic devices.
Currently there is no single standard that addresses security assurance in the development and delivery of IP. The charter of the IPSA working group is to provide a security assurance standard for hardware IP and its associated components to address security risks when integrated into embedded systems. It is the goal of the Accellera IPSA WG to define an automated systematic approach that can be consistently supported across multiple target implementations to eliminate possible security vulnerabilities during chip design.
“In today’s ‘connected’ world where data breaches and cyber attacks are a daily occurrence, semiconductors must be designed and delivered with security as a top priority” said Michael Munsey, Vice President of Business Development and Strategic Accounts at Methodics. “Accellera has a long history of organizing and leading collaborative working groups and has already developed a wide range of standards that have been successfully adopted throughout the electronics industry. In this important area covering semiconductor security standards, Methodics is proud to be a member of Accellera, working alongside such notable industry leaders as Cadence, Synopsys, Mentor, ARM, AMD, Intel, Qualcomm, and other members.”
There is a certain level of risk when integrating third-party IP (3PIP) into Silicon. The risk stems from unknown behaviors that may occur once integrated, which could result as an exploitable vulnerability. Silicon providers need a security assurance standard for acceptance before integrating 3PIP in order to minimize risk in their products.
With this new standard, user companies will have high confidence that IPs have addressed security concerns at the integration level and that user companies will be able to select the best tool(s) and IP(s) from competing vendors to achieve the best results for their products.
“By being an active member of Accellera, we can be sure that our ongoing IPLM development efforts continue to align with the emerging standards coming from Accellera. An important goal for Methodics is to remain current with new technologies and standards so that customers can continue to have a secure and protected environment for their IP while also providing interoperability with EDA tools and third-party IP,” concluded Michael.