Semiconductor IPs have an “attack surface” that indicates how they can be compromised in real world scenarios. Some portions of the attack surfaces are well known, others are discovered during analysis, testing or out in the field. SoCs that use large collections of IPs need a systematic and reliable way to determine the various security vulnerabilities across the hierarchy even as these vulnerabilities are discovered in heterogenous environments.
This webinar presented a methodology for IP analyzers and test teams to convey the security threats detected, and for SoC managers to consolidate and measure these threats in a systematic manner.
Click here to view a recording of this webinar.