Methodics
Methodics

SOC DESIGN PARTITIONING TO SAVE TIME AND AVOID MISTAKES

I started designing ICs in 1978 and continued through 1986, and each chip used hierarchy and partitioning but our methodology was totally ad-hoc, and documented on paper, so it was time consuming to make revisions to the chip or train someone else on the history or our chip, let alone re-use any portion of our chips again. Those old, manual ways of doing …

>> Read More at SemiWiki