SOC design complexity is rapidly increasing beyond the capabilities of existing engineering environments. Data sizes are increasing, and market windows are unforgiving, together these trends exacerbate the already exacting need to define, deliver, and test components assembled from many different design and IP acquisition flows. Avoiding mistakes and their resultant delays is critical. The inefficiencies that have been tolerated in existing flows are no longer acceptable.
The Percipient IP Lifecycle Management Platform (IPLM) mitigates complexity through automation and centralization of SOC development flows. Percipient provides traceability and a central source of truth that reflects the real time state of all projects across multi-site world wide organizations. Percipient tracks the exact design state as well as providing a platform for This built in traceability is the basis for further integration of third party tools. Bug tracking, requirements management data, customer in house databases, any and all can be easily tied to the exact state of the SOC development effort in real time through automation.
Increasing data volume is addressed with Warpstor, Methodic’s Enterprise Data Storage Acceleration solution. Warpstor virtualizes data delivery, generating fully functioning multi terabyte workspaces in seconds. With Warpstor only modified portions of the data need be transferred, even on initial workspace build. This means consumer wait time is greatly reduced, data storage requirements are minimized, and data transfer demands are lowered.
Challenges in verification and characterization of SOC designs can be optimized with Arrow, Methodics’ scalable massively parallel job execution platform. Arrow manages resource allocation based on availability and past requirements, ensuring the most efficient use of available assets. Paired with Warpstor Arrow becomes a foundation for cloud based resource utilization.
For more information on Methodics SOC design solutions please download the following whitepapers:
Traceability for the Design Verification Process