Methodics
Methodics

Verification Traceability

Verification Traceability seeks to definitively answer the following questions for a given snapshot of a design –

  • Which tests were run
  • Who ran these tests and where
  • What was the status of each of these tests
  • What was the coverage generated by these tests

This information should be automatically tracked, accurate and easily extractable from the system that manages the design. However, this task has become significantly more complex over time as the number of methodologies for verifying a design has proliferated. For most semiconductor designs, in addition to traditional test and regression runs, teams now have the option of running formal verification tools, hardware / software co-simulation and even AI based multi-run debug methods.

Adding to the complexity posed by proliferating methodologies, there is also a proliferation of platforms. Verification often split across geographies, across on-premises and cloud compute farms, and across teams using hardware acceleration. Multiplying methodologies and platforms thus pose a daunting challenge for collecting and analyzing the data that can answer the questions posed above.

Adding to the complexity posed by proliferating methodologies, there is also a proliferation of platforms. Verification often split across geographies, across on-premises and cloud compute farms, and across teams using hardware acceleration. Multiplying methodologies and platforms thus pose a daunting challenge for collecting and analyzing the data that can answer the questions posed above.

Determining the exact verification performed on key design snapshots is required to meet the stringent specifications of Automotive, Aerospace, or Medical industries, among others. Accurate project status reporting also demands easy and automatic verification results in the form of project dashboards.

The Percipient IP Lifecycle Management (IPLM) platform is built to enable teams to manage and provide easy, end-to-end verification traceability despite the complex nature of modern design verification using three key concepts

IP-Centric Design Methodology

Percipient provides a platform to manage designs as a collection of IPs. Each logical design block can be treated as a potentially reusable IP, even if the block is not intended to be an IP in the traditional sense. By modeling each block in the system using Percipient’s enhanced IP Model, users can track each block every time it is used in any chip or project automatically. This is true for foundation blocks used across several projects, and highly specialized blocks that are custom built for a single project.

Managed Workspaces

The second key concept is that Percipient builds and manages workspaces across users and projects. Every IP in the system is instantiated in one or more workspaces – sometimes by itself, other times in the context of different projects. Workspaces are created by individual designers debugging an IP or by workflows running advanced simulations and test methodologies at sub-system and project levels. Under all these conditions, across all platforms, Percipient keeps track of which version of which IP was instantiated in which workspace and by whom.

Annotating IPs with Verification Results

When verification is run in these workspaces, Percipient can be used as a single, unified location to annotate results. Thus verification performed by different methodologies, across different platforms, are all collated and visible on the IPs and IP Versions as one comprehensive single source.

Thus, all consumers of verification status and information – be it teams dedicated to ISO 26262 compliance, legal and finance teams looking to verify testing, project management looking for exact status – can all find complete, traceable information in one location.

Resources:

For more information on Methodics Verification Traceability solutions, please download the following whitepapers:

Traceability for the Design Verification Process

Meeting the ISO 26262 Traceability Requirement in Automotive Electronics Design